A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix

A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix

In this paper, a high-resolution time-to-digital converter (TDC) based on a field programmable gate array (FPGA) device is proposed and tested. During the implementation, a new architecture of TDC is proposed which consists of a measurement matrix with 1024 units. The utilization of routing resources as the delay elements distinguishes the proposed design from other existing designs, which cont...

LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging

The LinoSPAD camera system is a modular, compact and versatile time-resolved camera system, combining a linear 256 high fill factor pixel CMOS SPAD (single-photon avalanche diode) sensor with an FPGA (field-programmable gate array) and USB 3.0 transceiver board. This modularization permits the separate optimization or exchange of either the sensor front-end or the processing back-end, depending...

A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement

The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has b...

a new type-ii fuzzy logic based controller for non-linear dynamical systems with application to 3-psp parallel robot

abstract type-ii fuzzy logic has shown its superiority over traditional fuzzy logic when dealing with uncertainty. type-ii fuzzy logic controllers are however newer and more promising approaches that have been recently applied to various fields due to their significant contribution especially when the noise (as an important instance of uncertainty) emerges. during the design of type- i fuz...

Design of a FPGA based MPEG post-processing unit